Validation gates

Every gate this project runs, as gates.yaml declares it. A gate is declared at Phase 0 with the phase it starts at, so a subsystem has to specify its gates one phase ahead of implementing them, and roadmap validate fails a work package in the open phase that references a gate still at status declared.

Three statuses, and the required field set widens with each:

Status	Owes
declared	a unique id, a first phase, and a standing flag
specified	plus an assertion, what falsifies it, and its kind's fields
implemented	plus a test on disk and the command the phase-exit runner calls

just gate phase-exit <phase> runs every gate in force at a phase. A gate in that set which is not implemented fails the run rather than being skipped, because the registry already promised it at the phase it starts at.

The registry (143 gates)

Gate	First phase	Kind	Standing	Status	Owner
VAL-GATE-A11Y-001	P1	validation	yes	implemented	docs/design/ui-direction.md
VAL-GATE-ABC-001	6a17	invariant	no	declared	docs/design/back-office.md
VAL-GATE-ABSENT-SEAM-001	6a14	invariant	no	declared	docs/design/human-sustain.md
VAL-GATE-ACT-001	P1	policy	yes	implemented	docs/design/repo-craft.md
VAL-GATE-ADOPT-001	P5	invariant	no	declared	docs/design/repo-craft.md
VAL-GATE-AGT-001	P2	invariant	yes	specified	docs/design/ai-layer.md
VAL-GATE-ATP-001	6a12	invariant	no	declared	docs/design/back-office.md
VAL-GATE-AUTON-001	P6-W4	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-BATCH-001	P3i	invariant	no	declared	docs/design/production-quality.md
VAL-GATE-CAPA-001	6a11	invariant	no	declared	docs/design/production-quality.md
VAL-GATE-CART-001	P3g	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-CAU-001	CAUSAL	ground_truth	no	declared	docs/design/ai-layer.md
VAL-GATE-CAU-002	CAUSAL	ground_truth	no	declared	docs/design/ai-layer.md
VAL-GATE-CBAM-001	ECON	validation	no	declared	docs/design/back-office.md
VAL-GATE-CC-001	P0	validation	yes	implemented	CONTRIBUTING.md
VAL-GATE-CFG-001	P0	invariant	yes	implemented	docs/design/foundations.md 5.6
VAL-GATE-CI-001	P0	policy	yes	implemented	docs/design/repo-craft.md
VAL-GATE-CLA-001	P1	invariant	yes	implemented	CLA.md section 7
VAL-GATE-COLD-001	P3h	invariant	no	declared	docs/design/sensor-catalog.md
VAL-GATE-CONF-001	P6-W2	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-CONFTUT-001	P3	budget	no	declared	docs/design/repo-craft.md
VAL-GATE-COVER-001	P6-W6	invariant	no	declared	docs/design/roadmap.md
VAL-GATE-CV-001	P4	invariant	no	declared	docs/design/twin-core.md
VAL-GATE-DATA-001	P6-W6	invariant	no	declared	docs/design/foundations.md
VAL-GATE-DEMO-001	P1	budget	yes	implemented	docs/design/repo-craft.md
VAL-GATE-DET-001	P0	invariant	yes	implemented	docs/design/foundations.md 5.2
VAL-GATE-DET-002	P0	invariant	yes	implemented	docs/design/foundations.md 5.2
VAL-GATE-DOC-001	P1	invariant	yes	implemented	docs/DOCUMENTATION-STANDARD.md
VAL-GATE-DOCSITE-001	P3	policy	no	declared	docs/design/repo-craft.md
VAL-GATE-DORA-001	6a15	invariant	no	declared	docs/design/back-office.md
VAL-GATE-DRIFT-001	P6-W2	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-E1-001	P2	invariant	yes	specified	docs/design/dashboard-replay.md
VAL-GATE-ECO-001	P6-W3	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-EDGE-001	P6-W1	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-EHB-001	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-EHB-002	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-EHB-003	P3	validation	no	declared	docs/design/lss-engine.md
VAL-GATE-EHB-004	6a11	validation	no	declared	docs/design/production-quality.md
VAL-GATE-EHB-005	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-ENG-001	P3b	invariant	no	declared	docs/design/twin-core.md
VAL-GATE-ENV-001	P0	invariant	yes	implemented	docs/design/foundations.md 5.5
VAL-GATE-EPCIS-001	P3	validation	no	declared	docs/design/iot-fleet.md
VAL-GATE-ERG-SEAM-001	6a10	invariant	no	declared	docs/design/human-sustain.md
VAL-GATE-ESG-001	P6-W5	invariant	no	declared	docs/design/back-office.md
VAL-GATE-FCST-001	P3d	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-FCST-002	P3d	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-FED-001	P6-W3	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-FIN-001	ECON	invariant	no	declared	docs/design/back-office.md
VAL-GATE-FINOPS-001	P6-W5	invariant	no	declared	docs/design/back-office.md
VAL-GATE-FVA-001	6a16	invariant	no	declared	docs/design/back-office.md
VAL-GATE-GL-001	6a17	invariant	no	declared	docs/design/back-office.md
VAL-GATE-GLEC-001	P3h	validation	no	declared	docs/design/planning-supply.md
VAL-GATE-GNN-001	P6-W2	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-GOV-001	ECON	invariant	no	declared	docs/design/back-office.md
VAL-GATE-HEIN-001	6a10	invariant	no	declared	docs/design/human-sustain.md
VAL-GATE-HIL-001	P6-W1	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-HR-001	6a14	invariant	no	declared	docs/design/human-sustain.md
VAL-GATE-INJ-001	P3	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-INJ-002	6a11	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-INS-001	P6-W5	invariant	no	declared	docs/design/back-office.md
VAL-GATE-INV-001	P3d	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-IPH-001	P0	policy	yes	implemented	docs/design/repo-craft.md
VAL-GATE-LEDGER-001	P6-W4	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-LIC-001	P0	policy	yes	implemented	docs/design/repo-craft.md
VAL-GATE-MAS-001	P6-W4	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-MEIO-001	P3h	ground_truth	no	declared	docs/design/planning-supply.md
VAL-GATE-MEIO-002	P3h	validation	no	declared	docs/design/planning-supply.md
VAL-GATE-MSA-001	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-MSA-002	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-MTB-001	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-MTB-002	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-MTB-003	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-MTLS-001	P5	invariant	no	declared	docs/design/repo-craft.md
VAL-GATE-MULTI-001	P6-W3	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-NETDES-001	P6-W3	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-NIOSH-001	6a10	validation	no	declared	docs/design/human-sustain.md
VAL-GATE-NIST-001	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-NIST-002	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-NIST-003	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-NIST-004	P3	validation	no	declared	docs/design/lss-engine.md
VAL-GATE-NPV-001	6a17	invariant	no	declared	docs/design/back-office.md
VAL-GATE-NTIER-001	RISK	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-OEE-001	P3i	invariant	no	declared	docs/design/production-quality.md
VAL-GATE-OPCUA-001	P5	validation	no	declared	docs/design/iot-fleet.md
VAL-GATE-OPT-001	P3b	invariant	no	declared	docs/design/twin-core.md
VAL-GATE-ORDER-001	6a12	invariant	no	declared	docs/design/back-office.md
VAL-GATE-OTA-001	P6-W1	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-OTIF-001	P3e	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-OTSEC-001	OTDRILL	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-P2P-001	6a13	invariant	no	declared	docs/design/back-office.md
VAL-GATE-PDM-001	P3	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-PERF-001	P3	budget	yes	declared	docs/design/repo-craft.md
VAL-GATE-PERFORD-001	6a12	invariant	no	declared	docs/design/back-office.md
VAL-GATE-PM-001	P3c	ground_truth	no	declared	docs/design/lss-engine.md
VAL-GATE-PM-002	P3c	ground_truth	no	declared	docs/design/lss-engine.md
VAL-GATE-PM-003	P3c	validation	no	declared	docs/design/lss-engine.md
VAL-GATE-PROMO-001	6a16	invariant	no	declared	docs/design/back-office.md
VAL-GATE-PROV-001	P1	validation	yes	implemented	docs/design/repo-craft.md
VAL-GATE-QS-001	P1	budget	yes	specified	docs/design/repo-craft.md
VAL-GATE-RECALL-001	6a11	budget	no	declared	docs/design/production-quality.md
VAL-GATE-RECALL-002	P6-W3	budget	no	declared	docs/design/production-quality.md
VAL-GATE-REG-001	P0	invariant	yes	implemented	docs/testing-policy.md
VAL-GATE-REL-001	P0	validation	yes	implemented	docs/design/foundations.md 5.8
VAL-GATE-RELBUD-001	P1	budget	yes	specified	docs/design/roadmap.md 7.5
VAL-GATE-RET-001	P3f	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-RF-001	P3	validation	no	declared	docs/design/sensor-catalog.md
VAL-GATE-RF-002	P3	validation	no	declared	docs/design/sensor-catalog.md
VAL-GATE-RL-001	P6-W2	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-RMAP-001	P0	invariant	yes	implemented	docs/design/roadmap.md 7.4
VAL-GATE-RNG-001	P0	invariant	yes	implemented	docs/design/variability-and-faults.md A.7
VAL-GATE-ROST-001	ROST	invariant	no	declared	docs/design/human-sustain.md
VAL-GATE-RPO-001	6a15	invariant	no	declared	docs/design/back-office.md
VAL-GATE-RST-001	RISK	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-RULA-001	6a10	validation	no	declared	docs/design/human-sustain.md
VAL-GATE-RUNBOOK-001	P6-W5	invariant	no	declared	docs/design/back-office.md
VAL-GATE-SAST-001	P1	policy	yes	implemented	docs/design/repo-craft.md
VAL-GATE-SCH-001	P0	invariant	yes	implemented	docs/design/foundations.md 5.5
VAL-GATE-SEC-001	P0	validation	yes	implemented	CONTRIBUTING.md
VAL-GATE-SIM-001	P2	ground_truth	no	specified	docs/design/lss-engine.md
VAL-GATE-SLM-001	P6-W1	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-SMED-001	P3i	invariant	no	declared	docs/design/production-quality.md
VAL-GATE-SNF-001	P4	invariant	no	declared	docs/design/twin-core.md
VAL-GATE-SOE-001	SOE	invariant	no	declared	docs/design/back-office.md
VAL-GATE-SOP-001	6a16	invariant	no	declared	docs/design/back-office.md
VAL-GATE-SOPGEN-001	P6-W4	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-SPARK-001	P1	validation	no	specified	docs/design/iot-fleet.md
VAL-GATE-SPARK-002	P3	validation	no	declared	docs/design/iot-fleet.md
VAL-GATE-SPEND-001	6a13	invariant	no	declared	docs/design/back-office.md
VAL-GATE-SUP-001	P3e	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-SURR-001	P6-W2	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-TAR-001	ECON	invariant	no	declared	docs/design/back-office.md
VAL-GATE-TIER-001	P1	invariant	yes	implemented	docs/design/foundations.md
VAL-GATE-VAR-001	6a17	invariant	no	declared	docs/design/back-office.md
VAL-GATE-VLM-001	P6-W2	invariant	no	declared	docs/design/ai-layer.md
VAL-GATE-VMI-001	P6-W3	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-VSM-001	P3c	invariant	no	declared	docs/design/lss-engine.md
VAL-GATE-WE-001	P2	validation	no	specified	docs/design/lss-engine.md
VAL-GATE-WEBHOOK-001	P3	invariant	no	declared	docs/design/iot-fleet.md
VAL-GATE-WX-001	P6-W5	invariant	no	declared	docs/design/back-office.md
VAL-GATE-XDOCK-001	P3g	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-YARD-001	P3d	invariant	no	declared	docs/design/planning-supply.md
VAL-GATE-Z14-001	6a11	validation	no	declared	docs/design/production-quality.md
VAL-GATE-ZONE-001	6a15	invariant	no	declared	docs/design/back-office.md

What each gate asserts

VAL-GATE-A11Y-001

Asserts. axe-core reports zero critical and zero serious violations, the demo path is completable by keyboard alone, severity is encoded by shape and by text and never by color alone, and reduced motion is honored.

Falsified by. One critical or serious axe-core violation, one demo step unreachable by keyboard, or one severity encoded by color alone.

Reference. Web Content Accessibility Guidelines 2.1, W3C recommendation, level AA. https://www.w3.org/TR/WCAG21/

Runs. just a11y, tested by packages/twinflow-dashboard/tests/test_accessibility_floor.py, packages/twinflow-dashboard/tests/browser/axe-gate.mjs.

VAL-GATE-ABC-001

Declared at 6a17, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ABSENT-SEAM-001

Declared at 6a14, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ACT-001

Asserts. Every action a workflow uses is pinned to a commit SHA, and the workflow security audit reports no finding that .github/zizmor.yml does not record a reason for.

Falsified by. One action pinned to a tag or branch, or one audit finding with no recorded reason.

Runs. uv run pytest tests/test_workflow_supply_chain.py -q, tested by tests/test_workflow_supply_chain.py.

VAL-GATE-ADOPT-001

Declared at P5, owned by docs/design/repo-craft.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-AGT-001

Asserts. From v0.3.0 onward the E27 eval suite runs at every tag, accuracy and the abstention rate are recorded in the release notes, and accuracy above the abstention threshold is at least 0.98.

Falsified by. A tag whose release notes carry no eval figures, or accuracy above the abstention threshold below 0.98.

VAL-GATE-ATP-001

Declared at 6a12, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-AUTON-001

Declared at P6-W4, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-BATCH-001

Declared at P3i, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CAPA-001

Declared at 6a11, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CART-001

Declared at P3g, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CAU-001

Declared at CAUSAL, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CAU-002

Declared at CAUSAL, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CBAM-001

Declared at ECON, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CC-001

Asserts. Every commit since the previous tag parses as a conventional commit with a type from the set scripts/hooks/commit-msg declares, and the semver bump those types imply is the bump the tag being cut makes over the previous one.

Falsified by. One commit message that does not parse, or a tag whose bump is smaller than the commit types since the previous tag make honest.

Reference. Conventional Commits 1.0.0. https://www.conventionalcommits.org/en/v1.0.0/

Runs. uv run python scripts/checks/commit-message-gate.py --all, tested by tests/test_commit_message_gate.py.

VAL-GATE-CFG-001

Asserts. Every shipped config validates and every invalid fixture produces a line-numbered error carrying a suggestion. Meta-schema conformance belongs to VAL-GATE-SCH-001, whose tests call check_schema against the $schema each registry schema names, and is not restated here: two gates claiming one check means neither is read when it moves.

Falsified by. A shipped config that fails to load, or an invalid fixture whose error carries no line number or no suggestion.

Runs. uv run pytest packages/twinflow-config/tests/test_config_validation.py -q, tested by packages/twinflow-config/tests/test_config_validation.py.

VAL-GATE-CI-001

Asserts. A GitHub Actions workflow runs lint, the type check, and the test tiers on every pull request, across the declared interpreter matrix, and one aggregate job depends on every leg so a skipped leg cannot read as a pass. Whether that aggregate job is required for merge is branch protection state, which no checkout can read; the Scorecard Branch-Protection check is what reports it.

Falsified by. A pull request that merges with no CI run, or a matrix leg named in the workflow that never executes.

Runs. uv run python scripts/checks/ci-matrix-gate.py, tested by tests/test_ci_matrix_gate.py.

VAL-GATE-CLA-001

Asserts. The contributor agreement job passes the three checks CLA.md section 7 names: the pull request author's handle is in the signatories list, every signatory line matches the published expression, and every commit carries a Signed-off-by trailer.

Falsified by. A pull request that merges having failed any of the three checks.

Runs. uv run pytest tests/test_cla_gate.py -q, tested by tests/test_cla_gate.py.

VAL-GATE-COLD-001

Declared at P3h, owned by docs/design/sensor-catalog.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CONF-001

Declared at P6-W2, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CONFTUT-001

Declared at P3, owned by docs/design/repo-craft.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-COVER-001

Declared at P6-W6, owned by docs/design/roadmap.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-CV-001

Declared at P4, owned by docs/design/twin-core.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-DATA-001

Declared at P6-W6, owned by docs/design/foundations.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-DEMO-001

Asserts. The ten-minute scripted demo runs headless and green in under 600 seconds, with each scripted beat asserting on an observable rather than on a sleep.

Falsified by. A run over 600 seconds, or one beat that asserts on a sleep.

Noise floor. The run-to-run standard deviation of the demo wall time over five runs on the reference runner, published beside the measured value.

Runs. just demo, tested by tests/test_demo.py.

VAL-GATE-DET-001

Asserts. Two runs at the same run seed, the same config, the same platform, and the same pinned dependency set produce byte-identical event logs, per doctrine D-05 tier one.

Falsified by. One differing byte between the two event logs.

Runs. just determinism, tested by packages/twinflow-kernel/tests/test_scenario.py, packages/twinflow-rng/tests/test_derive.py, packages/twinflow-rng/tests/test_rng_known_answers.py.

VAL-GATE-DET-002

Asserts. Two runs at the same run seed and config on different platforms produce identical business events, and every continuous field agrees within the tolerance this file carries from measured divergence. The observed maximum divergence is published on every run.

Falsified by. A business event that differs across platforms, or a continuous field outside the recorded tolerance once that tolerance exists.

Noise floor. Not yet measured. The first two-platform run sets it, and until that run exists the gate publishes divergence and asserts no bound.

Runs. uv run pytest tests/test_compare_runs.py -q, tested by tests/test_compare_runs.py.

VAL-GATE-DOC-001

Asserts. The docs link check passes, the prose gate reports zero errors, and every filled metric marker resolves to a committed artifact under artifacts/measured/ that names its tool, seed, and run id. From v0.3.0 the first three lines of README carry the E1 replay URL and exactly one metric marker resolving to a headline_metric in ops.release.tagged.v1, which is the tag the bundle and the seeded number first exist at. The docs site build is asserted by VAL-GATE-DOCSITE-001 from v0.4.0, per docs/design/roadmap.md 5.3.

Falsified by. A broken link, one prose gate finding, a number in the docs that no committed artifact produced, or from v0.3.0 an opening README that carries no replay URL or more than one metric marker.

Runs. uv run python scripts/checks/docs-gate.py, tested by tests/test_docs_gate.py.

VAL-GATE-DOCSITE-001

Declared at P3, owned by docs/design/repo-craft.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-DORA-001

Declared at 6a15, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-DRIFT-001

Declared at P6-W2, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-E1-001

Asserts. From v0.3.0 onward the E1 replay bundle is re-recorded from the code of the tag being cut, the static viewer loads it, and the bundle's agent transcript passes the grounding checker.

Falsified by. A tag that publishes a bundle recorded from earlier code, a viewer that fails to load it, or a transcript the grounding checker rejects.

VAL-GATE-ECO-001

Declared at P6-W3, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-EDGE-001

Declared at P6-W1, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-EHB-001

Asserts. The center line and both control limits match every digit the handbook prints, to half a unit in the last printed place, using the published unbiasing constants, and the sample mean and sample standard deviation underneath those limits reach log relative error 13 against the StRD univariate sets. Both figures are reported, so a pass on the printed check that fails the estimator check is visible.

Falsified by. Any published digit that disagrees at the printed tolerance, or an underlying estimator below log relative error 13.

Reference. NIST/SEMATECH e-Handbook of Statistical Methods, section 6.3.2, What are Variables Control Charts?, the X-bar and R and individuals worked examples. The e-Handbook prints rounded results rather than certified ones, typically to four significant figures, which is why this gate carries two tolerances and reports both. https://www.itl.nist.gov/div898/handbook/pmc/section3/pmc32.htm

VAL-GATE-EHB-002

Asserts. Cp, Cpk, Pp, Ppk, the sigma level, and DPMO match every printed digit to half a unit in the last printed place, and the mean and standard deviation feeding each index reach log relative error 13 against StRD. Both figures are reported.

Falsified by. Any published digit that disagrees at the printed tolerance, or an underlying estimator below log relative error 13.

Reference. NIST/SEMATECH e-Handbook of Statistical Methods, section 6.1.6, What is Process Capability?, the capability worked example, which prints Cpk as 0.6667 and Cpl as 1.3333. https://www.itl.nist.gov/div898/handbook/pmc/section1/pmc16.htm

VAL-GATE-EHB-003

Declared at P3, owned by docs/design/lss-engine.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-EHB-004

Declared at 6a11, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-EHB-005

Asserts. The EWMA statistic and its variance-adjusted limits match every printed digit to half a unit in the last printed place, and the recursion reaches log relative error 12 against a closed-form expansion of the same weights. Both figures are reported.

Falsified by. Any published digit that disagrees at the printed tolerance, or a recursion below log relative error 12 against the closed form.

Reference. NIST/SEMATECH e-Handbook of Statistical Methods, section 6.3.2.4, EWMA Control Charts, the worked EWMA example. https://www.itl.nist.gov/div898/handbook/pmc/section3/pmc324.htm

VAL-GATE-ENG-001

Declared at P3b, owned by docs/design/twin-core.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ENV-001

Asserts. Every event carries producer_id, the sequence number is dense per (run_id, producer_id), and (sim_ts, producer_id, seq) is a total order over the log, per doctrine D-07.

Falsified by. A gap in the sequence, a duplicate, or a tie in the total order.

Runs. uv run pytest packages/twinflow-schemas/tests/test_log_invariants.py -q, tested by packages/twinflow-schemas/tests/test_log_invariants.py.

VAL-GATE-EPCIS-001

Declared at P3, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ERG-SEAM-001

Declared at 6a10, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ESG-001

Declared at P6-W5, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-FCST-001

Declared at P3d, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-FCST-002

Declared at P3d, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-FED-001

Declared at P6-W3, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-FIN-001

Declared at ECON, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-FINOPS-001

Declared at P6-W5, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-FVA-001

Declared at 6a16, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-GL-001

Declared at 6a17, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-GLEC-001

Declared at P3h, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-GNN-001

Declared at P6-W2, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-GOV-001

Declared at ECON, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-HEIN-001

Declared at 6a10, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-HIL-001

Declared at P6-W1, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-HR-001

Declared at 6a14, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-INJ-001

Declared at P3, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-INJ-002

Declared at 6a11, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-INS-001

Declared at P6-W5, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-INV-001

Declared at P3d, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-IPH-001

Asserts. No client name, employer name, internal document, or proprietary dataset appears anywhere in the tracked tree or in the commit history.

Falsified by. One banned term found in a tracked file or a commit message.

Runs. uv run python scripts/checks/banned-terms-gate.py --all, tested by tests/test_banned_terms_gate.py.

VAL-GATE-LEDGER-001

Declared at P6-W4, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-LIC-001

Asserts. The repository root carries a license file whose bytes match the published Apache-2.0 text, and every distributed package carries the same file and the NOTICE beside it.

Falsified by. A missing license file, or one byte different from the published text.

Reference. Apache License 2.0. https://www.apache.org/licenses/LICENSE-2.0.txt

Runs. uv run python scripts/checks/license-bytes-gate.py, tested by tests/test_license_bytes_gate.py.

VAL-GATE-MAS-001

Declared at P6-W4, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-MEIO-001

Declared at P3h, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-MEIO-002

Declared at P3h, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-MSA-001

Asserts. The full ANOVA table and the %Study Var, %Tolerance, and ndc figures match every digit the manual prints, to half a unit in the last printed place.

Falsified by. Any printed figure that disagrees at the printed tolerance.

Reference. AIAG Measurement Systems Analysis Reference Manual, 4th edition, the long-form ANOVA Gage R and R worked study, repeatability error term. The manual is sold rather than served, so the fixture encodes the study's data values only and the test docstring cites the edition and the table caption instead of reprinting the table. This repository has not retrieved the primary text and does not state its numbers as independently established fact. https://www.aiag.org/store/publications/details?ProductCode=MSA-4

VAL-GATE-MSA-002

Asserts. Both error-term results are printed side by side in the capability report, so the choice of error term is visible rather than hidden, and each matches its own source to the printed place.

Falsified by. Either result disagreeing with its source at the printed tolerance, or a report that prints one error term without the other.

Reference. AIAG Measurement Systems Analysis Reference Manual, 4th edition, Appendix A convention, operator-by-part interaction error term, cross-checked against the R package SixSigma, function ss.rr with errorTerm set to interaction, on the same data. https://www.aiag.org/store/publications/details?ProductCode=MSA-4

VAL-GATE-MTB-001

Asserts. The proportions, the center line, and the variable control limits match every printed digit to half a unit in the last printed place.

Falsified by. Any printed digit that disagrees at the printed tolerance.

Reference. Minitab p-chart documentation example. The dataset is encoded in the test suite and the docstring cites the page; nothing is redistributed in bulk. https://support.minitab.com/en-us/minitab/help-and-how-to/quality-and-process-improvement/control-charts/how-to/attributes-charts/p-chart/before-you-start/example/

VAL-GATE-MTB-002

Asserts. The category ordering matches the cited page exactly, and the cumulative percentages match every printed digit to half a unit in the last printed place.

Falsified by. A category ordering that differs from the page, or any printed digit that disagrees at the printed tolerance.

Reference. Minitab Pareto chart documentation example. The dataset is encoded in the test suite and the docstring cites the page; nothing is redistributed in bulk. https://support.minitab.com/en-us/minitab/help-and-how-to/quality-and-process-improvement/quality-tools/how-to/pareto-chart/before-you-start/example/

VAL-GATE-MTB-003

Asserts. The statistic, the degrees of freedom, the p-value, and the confidence interval match to the printed place, and the assumption checker selects the same test the cited page used.

Falsified by. Any printed digit that disagrees at the printed tolerance, or an assumption checker that selects a different test than the page.

Reference. Minitab two-sample t and Mann-Whitney documentation examples. The datasets are encoded in the test suite and the docstring cites both pages; nothing is redistributed in bulk. https://support.minitab.com/en-us/minitab/help-and-how-to/statistics/basic-statistics/how-to/2-sample-t/before-you-start/example/

VAL-GATE-MTLS-001

Declared at P5, owned by docs/design/repo-craft.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-MULTI-001

Declared at P6-W3, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-NETDES-001

Declared at P6-W3, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-NIOSH-001

Declared at 6a10, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-NIST-001

Asserts. Log relative error of the mean, the standard deviation, and the lag-1 autocorrelation against the certified values is at least 13 digits on every listed set except NumAcc4, where at least 10 is asserted and the shortfall is documented in the test docstring.

Falsified by. Any listed set whose log relative error falls below its stated floor.

Reference. NIST Statistical Reference Datasets, univariate summary statistics: Lottery, Lew, Mavro, Michelso, NumAcc1 to NumAcc4, and PiDigits, whose certified values are computed in multiple precision and published to 15 significant digits. https://www.itl.nist.gov/div898/strd/

VAL-GATE-NIST-002

Asserts. Log relative error of the F statistic and of the between and within mean squares is at least 10 on the low-difficulty sets and at least 8 on SmLs07 to SmLs09.

Falsified by. Any listed set whose log relative error falls below its stated floor.

Reference. NIST Statistical Reference Datasets, one-way analysis of variance: SiRstv, SmLs01 to SmLs09, and AtmWtAg. https://www.itl.nist.gov/div898/strd/

VAL-GATE-NIST-003

Asserts. Log relative error of every estimated coefficient and of the residual standard deviation is at least 7 on Filip and at least 10 on every other listed set, and the test docstring records the solver as QR or SVD.

Falsified by. Any coefficient below its floor, or a solver that reaches the estimates through the normal equations.

Reference. NIST Statistical Reference Datasets, linear regression: Norris, Pontius, NoInt1, NoInt2, Filip, Longley, and Wampler1 to Wampler5. https://www.itl.nist.gov/div898/strd/

VAL-GATE-NIST-004

Declared at P3, owned by docs/design/lss-engine.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-NPV-001

Declared at 6a17, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-NTIER-001

Declared at RISK, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-OEE-001

Declared at P3i, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-OPCUA-001

Declared at P5, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-OPT-001

Declared at P3b, owned by docs/design/twin-core.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ORDER-001

Declared at 6a12, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-OTA-001

Declared at P6-W1, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-OTIF-001

Declared at P3e, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-OTSEC-001

Declared at OTDRILL, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-P2P-001

Declared at 6a13, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PDM-001

Declared at P3, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PERF-001

Declared at P3, owned by docs/design/repo-craft.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PERFORD-001

Declared at 6a12, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PM-001

Declared at P3c, owned by docs/design/lss-engine.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PM-002

Declared at P3c, owned by docs/design/lss-engine.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PM-003

Declared at P3c, owned by docs/design/lss-engine.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PROMO-001

Declared at 6a16, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-PROV-001

Asserts. The release workflow builds every artifact twice from a pinned SOURCE_DATE_EPOCH and compares them byte for byte, attests SLSA build provenance over each one, and reads the PEP 740 attestation back off the index before the run is called successful.

Falsified by. Two builds of one commit that differ, an artifact published with no provenance attestation, or an index that serves no attestation for a published file.

Reference. SLSA v1.0 Build Level 3, and PEP 740 index support for digital attestations. https://slsa.dev/spec/v1.0/levels

Runs. uv run pytest tests/test_workflow_supply_chain.py -q -k provenance, tested by tests/test_workflow_supply_chain.py.

VAL-GATE-QS-001

Asserts. The five-minute quickstart runs from a clean container against the published instructions in under 300 seconds on the CI reference runner, ending on a live dashboard serving non-empty state, with no network access beyond the pinned image.

Falsified by. A run over 300 seconds, a run that needs a cloud account, or a dashboard serving empty state at the end of it.

Noise floor. The run-to-run standard deviation of the quickstart wall time over five runs on the reference runner, published beside the measured value.

VAL-GATE-RECALL-001

Declared at 6a11, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RECALL-002

Declared at P6-W3, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-REG-001

Asserts. Every commit since v0.1.0 whose type is fix touches at least one test file, or records a Regression-Test trailer giving at least twenty characters of reason why the defect has no test that could fail.

Falsified by. One fix commit that changes no test and carries no exemption trailer, or an exemption whose reason is shorter than the floor.

Reference. Conventional Commits 1.0.0, which defines fix as a commit that patches a bug. https://www.conventionalcommits.org/en/v1.0.0/

Runs. uv run python scripts/checks/regression-test-gate.py --range v0.1.0..HEAD, tested by tests/test_regression_test_gate.py.

VAL-GATE-REL-001

Asserts. CHANGELOG has a section for this tag, the semver bump matches the C9 policy for package APIs, REST and MCP contracts, event schemas, and facility.yaml, and the C6 compatibility table lists which recorded runs and configs this release loads.

Falsified by. A tag with no CHANGELOG section, or a bump that no C9 trigger in the same release record justifies.

Reference. Semantic Versioning 2.0.0, and Keep a Changelog 1.1.0. https://semver.org/spec/v2.0.0.html

Runs. uv run python scripts/checks/release-gate.py, tested by tests/test_release_gate.py.

VAL-GATE-RELBUD-001

Asserts. The release ritual completes inside the release wall-time budget on the pinned reference runner, and the measured duration is published on ops.release.tagged.v1 whatever it is.

Falsified by. A ritual run over the published budget on the reference runner.

Noise floor. The run-to-run standard deviation of the ritual duration over the releases cut so far, published beside the measured value.

VAL-GATE-RET-001

Declared at P3f, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RF-001

Declared at P3, owned by docs/design/sensor-catalog.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RF-002

Declared at P3, owned by docs/design/sensor-catalog.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RL-001

Declared at P6-W2, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RMAP-001

Asserts. roadmap validate, roadmap coverage, roadmap graph-lint, and roadmap drift all pass, zero requirement ids are unplaced, no issue carrying a req: label is closed as not planned, and no banned label exists in the repository.

Falsified by. An unplaced requirement id, a cycle in the work-package graph, a banned label, or a tracker state that disagrees with roadmap.yaml.

Runs. just roadmap-gate, tested by tools/roadmap/tests/test_roadmap.py, tools/roadmap/tests/test_completeness.py, tools/roadmap/tests/test_drift.py, tools/roadmap/tests/test_sync.py.

VAL-GATE-RNG-001

Asserts. Every draw in the 64-name known-answer corpus matches numpy exactly, and the corpus on disk is the corpus the generator produces, so a second language implementing A.7 has one frozen answer to meet rather than a negotiation with whatever Python does today.

Falsified by. One draw differing from the corpus, or a corpus that the generator no longer reproduces.

Reference. numpy's SeedSequence entropy mixing and the PCG64DXSM bit generator, which docs/design/variability-and-faults.md A.7 specifies the derivation against byte for byte. The registry carries this as VG-VAR-07 and foundations 7.3 states the same claim as RUST-1. https://numpy.org/doc/stable/reference/random/bit_generators/pcg64dxsm.html

Runs. uv run pytest packages/twinflow-rng/tests/test_rng_known_answers.py -q && uv run python tools/gen_rng_kat.py --check, tested by packages/twinflow-rng/tests/test_rng_known_answers.py, packages/twinflow-rng/tests/test_derive.py.

VAL-GATE-ROST-001

Declared at ROST, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RPO-001

Declared at 6a15, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RST-001

Declared at RISK, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RULA-001

Declared at 6a10, owned by docs/design/human-sustain.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-RUNBOOK-001

Declared at P6-W5, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SAST-001

Asserts. Static analysis runs over every language this repository ships and over its workflows, on a pull request and on a schedule, and its findings reach the repository security tab.

Falsified by. A language in the tree that no analysis covers, or a scan whose results are not published.

Runs. uv run pytest tests/test_workflow_supply_chain.py -q -k analysis, tested by tests/test_workflow_supply_chain.py.

VAL-GATE-SCH-001

Asserts. Producer and consumer contract tests pass, and the schema differ reports no field removal and no type narrowing within a major version.

Falsified by. A removed field or a narrowed type inside one major version.

Runs. uv run pytest packages/twinflow-schemas/tests/test_schema_registry.py -q, tested by packages/twinflow-schemas/tests/test_schema_registry.py.

VAL-GATE-SEC-001

Asserts. pip-audit and cargo-audit are clean or waived with an expiry date, every resolved dependency matches a row in the CONTRIBUTING.md allowlist including the MPL-2.0 row scoped to development dependencies, and the SBOM is attached to the release.

Falsified by. An unwaived advisory, a resolved dependency with no allowlist row, or a release with no SBOM attached.

Reference. The advisory database each tool names: the PyPI advisory database for pip-audit and the RustSec advisory database for cargo-audit, plus the SPDX license allowlist in CONTRIBUTING.md. https://github.com/pypa/advisory-database

Runs. uv run python scripts/checks/license-allowlist-gate.py, tested by tests/test_license_allowlist_gate.py, tests/test_workflow_supply_chain.py.

VAL-GATE-SIM-001

Asserts. The 95 percent confidence interval the engine reports for each variance component covers the injected truth in at least 91 of 100 runs, and the observed count is published whatever it is. The threshold is the exact one-sided binomial acceptance region rather than a chosen number: at n = 100 and alpha = 0.05, P(X <= 90) = 0.0282 rejects and P(X <= 91) = 0.0631 accepts, and the test docstring carries both probabilities.

Falsified by. Coverage at 90 of 100 or fewer for any variance component, or a run that does not publish its observed count.

Truth source. Repeated measures generated with injected operator variance, part variance, and repeatability, over the seed set recorded in the fixture.

Null model. An interval of the same nominal width placed at the grand mean, which covers the injected truth at chance for the variance components.

Noise floor. The seed-to-seed standard deviation of each estimated variance component, measured over the same 100 seeds and published.

VAL-GATE-SLM-001

Declared at P6-W1, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SMED-001

Declared at P3i, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SNF-001

Declared at P4, owned by docs/design/twin-core.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SOE-001

Declared at SOE, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SOP-001

Declared at 6a16, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SOPGEN-001

Declared at P6-W4, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SPARK-001

Asserts. The edge-node profile passes with zero failures against a device emitting NBIRTH, DBIRTH, NDATA, and NDEATH with metric aliasing.

Falsified by. One compatibility kit failure on the edge-node profile.

Reference. Eclipse Sparkplug specification version 3.0.0, dated 2022-11-16, and the Technology Compatibility Kit the Eclipse Sparkplug project publishes for it, edge node profile. https://projects.eclipse.org/projects/iot.sparkplug

VAL-GATE-SPARK-002

Declared at P3, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SPEND-001

Declared at 6a13, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SUP-001

Declared at P3e, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-SURR-001

Declared at P6-W2, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-TAR-001

Declared at ECON, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-TIER-001

Asserts. Every package in the uv workspace appears in the RA-a layer map with its ISA-95 level, its Purdue level, its compute tier, and its latency budget filled.

Falsified by. One unfilled cell in the layer map, or one package with no row.

Runs. uv run python scripts/checks/layer-map-gate.py, tested by tests/test_layer_map_gate.py.

VAL-GATE-VAR-001

Declared at 6a17, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-VLM-001

Declared at P6-W2, owned by docs/design/ai-layer.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-VMI-001

Declared at P6-W3, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-VSM-001

Declared at P3c, owned by docs/design/lss-engine.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-WE-001

Asserts. For each of the 8 Nelson tests and each of the 4 Western Electric zone rules, a hand-constructed minimal series triggers exactly that rule and no other, and a near-miss series triggers none.

Falsified by. Any series that triggers a second rule, or a near-miss series that triggers any rule.

Reference. Two rule sets the industry routinely conflates, cited separately. Lloyd S. Nelson, The Shewhart Control Chart, Tests for Special Causes, Journal of Quality Technology 16(4), 237 to 239, October 1984, for the eight tests. The Western Electric Statistical Quality Control Handbook for the four zone rules, which this gate names as the source and does not quote, its text not having been retrieved here. https://doi.org/10.1080/00224065.1984.11978921

VAL-GATE-WEBHOOK-001

Declared at P3, owned by docs/design/iot-fleet.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-WX-001

Declared at P6-W5, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-XDOCK-001

Declared at P3g, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-YARD-001

Declared at P3d, owned by docs/design/planning-supply.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-Z14-001

Declared at 6a11, owned by docs/design/production-quality.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

VAL-GATE-ZONE-001

Declared at 6a15, owned by docs/design/back-office.md. Its assertion is specified one phase before it is implemented, which is what stops a gate being written to fit the code that was going to be written anyway.

Exit sets by phase

Derived from the registry: every gate whose first phase is this one, plus every standing gate already in force. Never authored, so the phase table and the registry cannot disagree.

Phase	Gates in force
P0	14
P1	25
P2	39
P3	38
P3b	29
P3c	31
P3d	31
P3e	29
P3f	28
P3g	29
P3h	31
P3i	30
ECON	31
6a10	31
6a11	32
ROST	28
6a12	30
RISK	29
6a13	29
6a14	29
OTDRILL	28
6a15	30
CAUSAL	29
6a16	30
SOE	28
6a17	31
P4	29
P5	30
P6-W1	31
P6-W2	33
P6-W3	33
P6-W4	31
P6-W5	32
P6-W6	29